1. Field of the Invention
The present invention relates to a clock data recovery circuit and a method thereof, and more particularly to a clock data recovery circuit utilizing a phase selector for selecting an output clock as a feedback clock from a plurality of output clocks to reduce the cost of the clock data recovery circuit, and a method thereof.
2. Description of the Prior Art
Clock data recovery circuit can be utilized for receiving a digital data and generating a clock signal according to the digital data, wherein the clock signal generated by the clock data recovery circuit is synchronized with the digital data. Thus, in a communication system, the clock data recovery circuit is not only being utilized for recovering the clock signal carried by the digital data, but also being utilized for repairing the digital data. For example, the clock data recovery circuit can be utilized to reduce the digital data's noise, and to adjust the timing of the rising edge and the falling edge of the digital data. In addition, the clock data recovery circuit generates the clock signal according to a reference clock signal and the digital data, wherein the frequency of the reference clock signal is slower than the frequency of the clock signal.
Conventionally, the clock data recovery circuit is configured as a feedback loop. Firstly, the clock data recovery circuit generates a plurality of clock signals with different phases according to the reference clock signal. Then, the clock signals are inputted to a phase rotator. The phase rotator adjusts a specific phase upon all of the phases of the plurality of clock signals to generate a plurality of adjusted phases. Then, the digital data is compared with the plurality of adjusted phases to generate a plurality of compared results respectively. Then, the phase rotator further adjusts the specific phase according to the plurality of compared results in order to match the plurality of compared results with a predetermined combination. By doing so recursively, the clock signal generated by the phase rotator may synchronize with the clock signal of the digital data when the plurality of compared results are matched to the predetermined combination.
However, the cost of the above-mentioned clock data recovery circuit is expensive since the area occupied by the phase rotator is relatively large and the operation of the phase rotator is complicated. For example, if four different combinations of phases are required in the conventional clock data recovery circuit, wherein each combination is comprised of eight phases, then the phase rotator may comprise at least four 8-to-1 multiplexers, which may occupy quite a large area in the whole clock data recovery circuit. Therefore, providing a low cost clock data recovery circuit and therefore reducing the cost of a transceiver is a significant concern in the mixed signal field.